Q on SPI

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stevech
Posts: 715
Joined: 22 February 2006, 20:56 PM

Q on SPI

Post by stevech »

SPI slave devices' chip select (CS) ... is it required or just common practice to take CS false at the end of each n-byte transfer?

I speculate that some chips require CS false to signify no-more-bytes-coming. Or is there a spec/standard vs. this being chip-specific?
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dkinzer
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Posts: 3120
Joined: 03 September 2005, 13:53 PM
Location: Portland, OR

Re: Q on SPI

Post by dkinzer »

stevech wrote:SPI slave devices' chip select (CS) ... is it required or just common practice to take CS false at the end of each n-byte transfer?
There is no standard. Some devices require CS to go inactive in order to initiate an internal process (e.g. SPI Flash RAM devices) while others are happy to have CS active for an indefinite period of time. You have to read the datasheet for each SPI device of interest to determine what its requirements are.
- Don Kinzer
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stevech
Posts: 715
Joined: 22 February 2006, 20:56 PM

Post by stevech »

thanks. I suspected that.
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