There are no dedicated CS pins for SPI on the 1280 as there were on the 1281ae, right? It's not clear whether the 1280/1 requires them fixed in hardware, or if on the 1281ae the pin was just a designation for convenience.
EDIT: clarification: there is support for 4 HW ports, but only one defined CS is included. This actually is exactly the same, then, as the 1281. The (new) question is whether there's a difference between using user-defined CS pins, and the explicitly reserved CS.
I believe there is no difference. Here is the relevant text from the datasheet:
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start.
This means the VM must explicitly control the SS line (PB0) and could just as well do this for a user configured chip select pin.
The pin that with the SS designation is defined for use as an input when the device is an SPI slave. Any output pin can be used for SS when the device is an SPI master.
Currently, the ZBasic System Library functions do not support slave mode. One could write code for that mode for a native mode device.
No SPI issue here.
I'll search the forums to find what I too-vaguely remember about limitations of connecting SPI devices using the VM. Maybe nothing and I'm (again) hosed up.
There was an issue with early versions of the ENC28J60 which had to run SPI at 8MHz or use the same clock for it and the microcontroller. Maybe this is what you were remembering.