Fast I/O reading

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meenbombs
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Joined: 20 November 2008, 15:54 PM

Fast I/O reading

Post by meenbombs »

I am monitoring the trajectory of fast moving particles. I plan on using an array of phototransistors. I will have between 24 and 68 phototransistors per array and the particles will only cause an interuption in the phototransistors state for 10 microseconds. Properly programmed, is the ZX-1280n capable of reading the states of 68 separate pins and recognizing if one has changed for only 10 microseconds? Also, because the array will be split into an X and Y axis two pins will change at exactly the same time. Will the ZX be able to read at least two pins simultaneously or at least within the 10 microsecond timeframe. Thanks.
dkinzer
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Re: Fast I/O reading

Post by dkinzer »

meenbombs wrote:Will the ZX be able to read at least two pins simultaneously or at least within the 10 microsecond timeframe.
10uS is about 147 CPU cycles at 14.7MHz. It may be feasible to monitor a few I/O ports for 10uS pulses depending on what needs to be done when a pulse is detected.
- Don Kinzer
mikep
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Joined: 24 September 2005, 15:54 PM

Re: Fast I/O reading

Post by mikep »

Don is right. You only have 147 cycles to play with which may equate to only 78 instructions. The question is not so much whether the ZX1280n can do it but whether you can do it with any mega device - there isn't much time.

68 inputs means using 9 I/O ports. It would easier if you only had 64 inputs. You don't say if you need to see a pulse or just a transition. A transition would be easier.

XORing old and new values will help you recognize a transition. Two XORs ANDed together would help recognize a pulse.

If you need do to some additional processing every time you see a transition then it needs to be something very quick such as logging to RAM.

You may need to optimize this routine and use assembly language directly. See the #asm/#endasm directives in ZBasic.
Mike Perks
meenbombs
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Post by meenbombs »

I went back and did the transit time math again hoping I made an error and I would have 100 uSec. Typical of my luck I did do the math wrong, however, I only have 1 uSec. I think this might be the end of this project. I cannot think of a reliable hardware method of reducing the inputs appreciably or increasing the read time with one exception. I an probably assign each phototransistor a unique resistor value and use a ADC per array. How fast can the ZX line get an accurate ADC reading? I can also offset the X axis array from the Y axis array. That would allow me to read one array and then a few microseconds later read the other. Then I would only have to have one value to read at a time but the two readings would still be be 5 or 6 uSec apart. My gut tells me using ADC is going to be a bad idea but I am a little short on experience to make a decision based on my gut. Can anybody with some experience tell me one way or the other? I looked to the ZX line because I used a BX24 in a former life and wanted to stay with a similar language. If I am better off moving on to a different micro, an FPGA, or something else I would appreciate somebody telling me that too. Thanks for the help.
mikep
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Post by mikep »

meenbombs wrote:If I am better off moving on to a different micro, an FPGA, or something else I would appreciate somebody telling me that too.
FPGA

I just purchased this Spartan-3 development board from Digilent to use as the basis for a logic analyzer (see http://www.sump.org/projects/analyzer) and also to learn about FPGAs. I like it so much that I'm building a custom input level converter board for the logic analyzer - more about this hopefully in a few weeks.

BTW In case you didn't get the connection, you can use much of this open source logic analyzer code as the basis for your FPGA detection card. It includes a digital filter and a trigger logic.
Mike Perks
dkinzer
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Post by dkinzer »

meenbombs wrote:How fast can the ZX line get an accurate ADC reading?
An A-D conversion takes 13 ADC clock cycles in free-running mode and 25 ADC clock cycles from a standing start. The ADC clock is limited to the range of 50KHz to 200KHz and a limited number of prescaler choices is available to use as a divisor from the CPU clock. At 14.7MHz, the only usable prescaler is 128, yielding an ADC clock of 115.2KHz. At that clock rate, even a free-running ADC conversion will require 113uS.

Mike's suggestion of looking into an FPGA is a good one. Another idea that might work is to employ a flip-flop or latch that is set by the generated pulse and reset by the ZX. This would allow plenty of time for recognition of the change in state but there still may be an issue with the latency between when the pulse occurs and the latched event is detected.
- Don Kinzer
stevech
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Joined: 22 February 2006, 20:56 PM

Re: Fast I/O reading

Post by stevech »

meenbombs wrote:I am monitoring the trajectory of fast moving particles. I plan on using an array of phototransistors. I will have between 24 and 68 phototransistors per array and the particles will only cause an interuption in the phototransistors state for 10 microseconds. Properly programmed, is the ZX-1280n capable of reading the states of 68 separate pins and recognizing if one has changed for only 10 microseconds? Also, because the array will be split into an X and Y axis two pins will change at exactly the same time. Will the ZX be able to read at least two pins simultaneously or at least within the 10 microsecond timeframe. Thanks.
can you instead observe particle trails, as left in a humid atmosphere of the right kind of vapor?

Or buy/build a scintillator: this is a common gamma or x-ray particle detector. It converts the particle's energy to photons which can be easily measured. However, most such devices rely on multiple particles passing by and the device does a lot of integration. You'll see this in things like hand-held and portal (gate-in) radiation detectors sold in the marketplace.

I suspect that Scientific American published DIY on scintillators.
spamiam
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Post by spamiam »

dkinzer wrote:Another idea that might work is to employ a flip-flop or latch that is set by the generated pulse and reset by the ZX. This would allow plenty of time for recognition of the change in state but there still may be an issue with the latency between when the pulse occurs and the latched event is detected.
I like the idea of a latch or flip-flop. Almost certainly they will have a bandwidth of more than 1MHz, so a 1us spike can be detected.

But will your phototransistor respond to such a short impulse? Capacitance in the transistor and in the associated circuitry might be an issue.

-Tony
meenbombs
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Post by meenbombs »

I have taken to the latch idea (thank you all for the ideas). I am researching some latching multiplexers (I am not sure if there is an official name for them). That will allow me to move from the ZX 12xx to a ZX 40 or maybe even a 24. I don't expect there to be a problem with the phototransistors because to my surprise most of them run in the single to double digit nSec range. I don't need to know exactly when the particle passed, I just need to know that it did pass and where in the array it passed. So, even if a capacitance issue delays th signal I will still be fine. Thanks again for the help.
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