ZBasic Forum

Hi,
I need some help in the diagnostic why I am experiencing reading the LTC1296. The reading data do not match the voltage input. I am using the ShiftInEx(dataPin, clkPin, bitCnt, flags) with no success. I tried every combination possible in the Shiftin setup but every thing it is been unsuccessful to get a valid reading. To read the data I am setting the format to receive the data as the MSB and sent the command to send it back as MSB. But still the data it is not good. I wrote a manual routine to read it and read it perfectly with no problems. One problem that I see with the Shiftin command it is how to setup it if you want to read the data in the trailing or the leading. Using my routine it read the LTC data faultless and the counts reading coinciding with the input voltage. Right now ran out of ideas on how to solve the problem

I like to use the shiftin command because it require less instructions. Attached it is a file with both routine running on it. I am reading the ltc1296 input port 6.
Any help will be appreciate.

I am using the Scite version 1.62 compile version v4.3.14 Zbasic IDE v1.75

rosariote wrote:I am using the ShiftInEx(dataPin, clkPin, bitCnt, flags) with no success.

One problem is that the ShiftInEx() call specifies 11 clock cycles - it should be 12, I think.

Secondly, to reproduce something close to your working PulseOut()/GetPin() combination, you should probably configure ShiftInEx() to sample the input before the trailing edge. That would require a 'flags' parameter of &H0A.

Note that the PulseOut()/GetPin() combination actually samples after the trailing edge but the data hold time with respect to the falling edge of the clock could be an issue. The datasheet says that the hold time is typically 130 ns - that's only about two CPU cycles at 14.7MHz.

You could modify read_port_inp() to sample before the falling clock edge thus:

Hi,
I tried all the combination possible from the table page 238. The table shows all the options. If you select active clock edge that is the leading clock edge
&H00 you can see it is the same as the MSB = &H00. Something it is not right. So you can not select the trailing or the leading from the options.

Did a check by comparing both routine bits reading. Noticed that the bits using the ShiftInEx the bits are stored 3 bits off to the left. If I shift the variable by "shr" 3 times to the right the reading are goods. The reading matched the voltage reading from my voltmeter. Can you explained that. Just by shifting the variable 3 bits right the reading looked good. Normally I found out that most of the basics instructions reading the adc chips have the same problem and needed to use my routine. The problem reading adc it is the company makers do not follow an standard. Question: It is there is a way to find out how the instruction from the Zbasic it is done. I would like to see how it is done.
I am going to update my programs to use the ShiftInEx and shift the variable 3 times right. By doing so do not need to use my routine since it save some instructions.
Thank you for you help. It is late and tomorrow I will be doing some more testing to make sure the reading linearity from 0 to 5 volts are OKAY.

rosariote wrote:So you can not select the trailing or the leading from the options.

As with all "flags"-type parameters, individual bits or groups of bits have certain meanings. You combine them to get the desired result.

[table][mrow]Function[mcol]Bit pattern
[row]MSB first[col]&H00
[row]Sample input before the active clock edge[col]&H02
[row]The active edge is the trailing clock edge[col]&H08
[mrow]Combined value[mcol]&H0a
[/table]

The combination process is by "logical OR". This may be more clearly understood by looking at the Bit Mask column in the Control Flag Definitions table in the description of ShiftInEx(). The x characters in the bit masks means "don't care". From this, you can see that the least significant bit of the flags parameter controls the bit order, bit 1 controls sampling before/after the active edge and bit 3 controls which edge, leading or trailing, is the active edge.

rosariote wrote:Noticed that the bits using the ShiftInEx the bits are stored 3 bits off to the left.

That is how it works.

ShiftInEx Description wrote:If MSB order is specified, the first bit read will be in the most significant bit position of the result.

Hi,
I did not know what I was doing but tried the different combinations in the table with not luck as you explained. Like I said before. I encountered same problem with other basics micro reading ADC and end using my routine.
Today checked the voltage linearity and it is right on.

I would like to thank you for taking your time to give me some advice but I think there are nothing to do just shift the variable 3 times to the right to fix the problem.