I want to receive data from an SPI device remote from the ZX-24.
Is it feasible to extend,via wire, an SPI buss driven by a ZX-24 to a length not to exceed 1 meter?
Any enlightenment will be appreciated.
Vic
Length of SPI buss
Length of SPI buss
Vic Fraenckel
KC2GUI
windswaytoo ATSIGN gmail DOT com
KC2GUI
windswaytoo ATSIGN gmail DOT com
Re: Length of SPI buss
I don't have a definitive answer but, as always, the shorter the better. The article Serial Protocols Compared doesn't give a specific bus length limit but suggests that the maximum bus length for SPI is less than 10 ft. A post on the BasicX Yahoo group by Tom Becker indicates that he couldn't get a BX-24 to run with a 14" SPI bus extension.victorf wrote:Is it feasible to extend,via wire, an SPI buss driven by a ZX-24 to a length not to exceed 1 meter?
I'm certain that you could do 1 meter with a bit-banged SPI interface. The protocol isn't very complicated so it should b easy to implement. You can find BasicX code for bit-bang SPI on Prof. Anderson's site.
- Don Kinzer
SPI bus length
The bus length for SPI is very dependent on the clock speed. If the max clock speed is kept below a few hundred kHz the length can easily be 10 feet. With the multi MHz clock used by the processor to fetch instructions even one foot is pushing it unless the run is very low capacitance. Perhaps one of the new parts that keeps code in on-chip memory would allow some freedom to trade clock speed for distance since the max clock speed is not forced by the program memory.
Another possibility would be to buffer the SPI signals between the ZBasic module and the distant device. This would allow two benefits. First, the external SPI could be disabled when the clock rate must be high. Second, the wire could be driven by a part with something like full HC drive. The eeprom in particular has a low drive on the data which limits the capacitance that can be driven. Buffering it from the external SPI bus would allow more capacitance to be driven, limited by the buffer. Since the eeprom chip select is available it is easy to control the buffer.
Since every combination of parts gives a different maximum clock rate the ultimate answer is to just try higher clock rates until performance suffers and then back off a factor of four to give a conservative clock speed.
Another possibility would be to buffer the SPI signals between the ZBasic module and the distant device. This would allow two benefits. First, the external SPI could be disabled when the clock rate must be high. Second, the wire could be driven by a part with something like full HC drive. The eeprom in particular has a low drive on the data which limits the capacitance that can be driven. Buffering it from the external SPI bus would allow more capacitance to be driven, limited by the buffer. Since the eeprom chip select is available it is easy to control the buffer.
Since every combination of parts gives a different maximum clock rate the ultimate answer is to just try higher clock rates until performance suffers and then back off a factor of four to give a conservative clock speed.
mwf
Re: SPI bus length
Not a bad idea. Additionally, I understand that a lower impedance at the receiving end will lessen the effects of noise compared to a high impedance receiver.mwf wrote:The bus length for SPI is very dependent on the clock speed. If the max clock speed is kept below a few hundred kHz the length can easily be 10 feet. ...
Another possibility would be to buffer the SPI signals between the ZBasic module and the distant device.
So, would a 74HCT125 "line driver" have what it takes for this purpose?
-Tony
being single-ended, a distance constraint may be ground loops and ingested noise, given some shielding and the speed limit that comes from that cabling capacitance.
Shorter is better.
Slower is better.
Shielded is better.
Longer = use of a differential line driver/receiver for common mode rejection.
Shorter is better.
Slower is better.
Shielded is better.
Longer = use of a differential line driver/receiver for common mode rejection.
From a quick look, the best capacitor driver may be 74AC(T)125 with its high output current. The driver end of the wire would be driven from a few ohms then. Terminating the receiver end with some resistance might improve the settling time by a few nanoseconds. Probably not worth the trouble. A series resistor at the driver end (about 100 ohms for twisted pair) would also help settling time. Again, is it worth the bother since it buys so little increase in clock speed?
Differential signals help if there is a common mode noise problem. If the power and all other signals are routed such that there is little area covered by the cableing then there may not be much common mode noise. If, instead, the power comes from a different source at each end of the SPI run then the area of the ground loop (really signal plus ground loop in this case) may be large and the common mode noise may be high.
Most of the differential signaling chips only have a couple volts of common mode range so you need to beat down the common mode noise as much as you can. Otherwise, the differential signal can be corrupted by the noise and you don't have a lot to show for your trouble.
Differential signals help if there is a common mode noise problem. If the power and all other signals are routed such that there is little area covered by the cableing then there may not be much common mode noise. If, instead, the power comes from a different source at each end of the SPI run then the area of the ground loop (really signal plus ground loop in this case) may be large and the common mode noise may be high.
Most of the differential signaling chips only have a couple volts of common mode range so you need to beat down the common mode noise as much as you can. Otherwise, the differential signal can be corrupted by the noise and you don't have a lot to show for your trouble.
mwf