Hardware SPI support

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stevech
Posts: 715
Joined: 22 February 2006, 20:56 PM

Hardware SPI support

Post by stevech »

I read the prior postings discussing support/bugs in ZBasic for hardware SPI.

Does VM du jour support up to 4MHz SPI? If not, is there any speed constraint in the VM other than an efficient way to stream back-to-back bytes (both in and out)?
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dkinzer
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Posts: 3120
Joined: 03 September 2005, 13:53 PM
Location: Portland, OR

Re: Hardware SPI support

Post by dkinzer »

stevech wrote:I read the prior postings discussing support/bugs in ZBasic for hardware SPI.
I believe that the discussion related to a limitation of the hardware SPI interface with respect to certain devices that required their chip select to remain asserted over a number of transactions. The ZXs that use external EEPROM are not compatible with such devices because the SPI bus is shared. Even on ZXs that store the program in internal Flash, the SPI chip select is asserted only for the duration of a single call to SPICmd().
stevech wrote:Does VM du jour support up to 4MHz SPI?
The maximum attainable SPI clock speed is 1/2 of the CPU frequency or 7.3MHz. Some SPI devices cannot run that fast, though.
- Don Kinzer
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stevech
Posts: 715
Joined: 22 February 2006, 20:56 PM

Post by stevech »

I don't think I would have a problem..

This device I'm working with shows slave select as true throughout the typical multi-byte transaction: <op code><address1><address2><data>. So I merely ensure that I do all in a single SPICmd() call.

I suspect dropping SS forces the device to go to the state of expecting an op code.
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